1. Field of the Invention
The invention relates generally to a device configuration and manufacturing processes. More particularly, this invention relates to manufacturing processes enhanced by particular isolation/insulation structure to allow for completely decoupled high voltage and low voltage transistor manufacturing processes.
2. Description of the Relevant Art
The manufacturing processes and structural features of the high voltage and low voltage semiconductor devices are very different. Specifically, high voltage devices such as LDMOS, HV NMOS, HV PMOS transistors, HV PNP and HV NPN are structured with device components having larger dimensions on a wafer and die. The manufacturing processes for these devices require generally non-critical mask layers such as buried layer, high voltage (HV) wells, body regions, and first-polysilicon (1P) gates. In contrast, the low voltage devices such as low voltage CMOS transistors are manufactured with higher density. Therefore, the packing density of such devices within a die is of primary concern. In order to address such design issues, the low voltage transistors require the use of critical mask layers such as the second poly gate, contact, metal and via masks. The differences of dimensions and geometrical precision requirements between the high voltage and low voltage circuits can be as much as one order of magnitude. Such differences in structural features that may include the dimensional and precision control differences and also the difference of manufacturing processes significant increase the difficulties in attempt to integrate the low voltage and high voltage device on the same wafer. Further, the process for high voltage devices usually requires high temperature and long thermal cycles. Such high temperature long thermal process requirement would ruin the low voltage devices and process that is built on the same wafer.
In the meantime, there are ever increasing demands for routinely integrating the low voltage and high voltage device on the same wafer driven by the trend of SOC (System on Chip). Such integration provides the benefits of miniaturization, lower energy consumption and high level of functional integration.
According to above integrated device configurations and manufacturing processes, for manufacturing a HV-LV integrated device, the low voltage semiconductor manufacturing processes must be applied because the more dominated and more stringent requirements of the low voltage devices. For this reason, the production costs are increased due to the facts higher precision of alignment and control would also apply to the HV device structure and process that would otherwise be using lower precision of alignment and control. High temperature and long thermal cycles also prevent the integrations of many low voltage structures into HV structure.
Therefore, a need still exists in the fields of circuit design and device manufactures for providing a new and improved configuration and manufacturing method to resolve the above-discussed difficulties. Specifically, a need still exists to provide new and improved configuration to such that the manufacturing processes of the high voltage device is not subject to the requirements of the low voltage devices such that the unnecessary processing complications and increase of costs that usually occur in integrating the HV-LV transistors on the same wafer can be circumvented.